SPLLCM=0, SPLLSEL=0, SPLLVLD=0, SPLLEN=0, SPLLERR=0, LK=0, SPLLCMRE=0, SPLLSTEN=0
System PLL Control Status Register
| SPLLEN | System PLL Enable 0 (0): System PLL is disabled 1 (1): System PLL is enabled |
| SPLLSTEN | System PLL Stop Enable 0 (0): System PLL is disabled in Stop modes 1 (1): System PLL is enabled in Stop modes |
| SPLLCM | System PLL Clock Monitor 0 (0): System PLL Clock Monitor is disabled 1 (1): System PLL Clock Monitor is enabled |
| SPLLCMRE | System PLL Clock Monitor Reset Enable 0 (0): Clock Monitor generates interrupt when error detected 1 (1): Clock Monitor generates reset when error detected |
| LK | Lock Register 0 (0): Control Status Register can be written. 1 (1): Control Status Register cannot be written. |
| SPLLVLD | System PLL Valid 0 (0): System PLL is not enabled or clock is not valid 1 (1): System PLL is enabled and output clock is valid |
| SPLLSEL | System PLL Selected 0 (0): System PLL is not the system clock source 1 (1): System PLL is the system clock source |
| SPLLERR | System PLL Clock Error 0 (0): System PLL Clock Monitor is disabled or has not detected an error 1 (1): System PLL Clock Monitor is enabled and detected an error. System PLL Clock Error flag will not set when System OSC is selected as its source and SOSCERR has set. |